a) Field of the Invention
The present invention relates to a manufacture method of semiconductor devices, and more particularly to a manufacture method of semiconductor devices having fine MOS transistors.
b) Description of the Related Art
High integration and high speed are requisites for improvement on the performance of semiconductor integrated circuit devices. Therefore, MOS transistors which are typical semiconductor elements of integrated circuit devices are required to be made fine or small. Sizes of a MOS transistor are becoming small both in substrate surface and depth directions, e.g., a gate oxide film of 10 nm or thinner and a source-drain junction of 100 nm or shallower.
As MOS transistors are made fine, impurities are redistributed during thermal processes to cause the short channel effect (punch-through between the source and drain), or impurities in the gate electrode penetrate through the gate oxide film into the channel region. In order to solve these problems, it is generally required to use low temperature processes.
An interlayer or interlevel insulating film has been formed mostly by batch thermal CVD after a gate electrode and source/drain regions on both sides of the gate electrode are formed. To meet the need of low temperature processes, technology of forming an interlayer insulating film by plasma CVD (PECVD) or technology of forming it by single wafer processing type thermal CVD have been developed. It is sufficient for a substrate to be heated to about 300.degree. C. to 550.degree. C. during plasma CVD.
Dual-gate surface channel MOSFETs, with p-type impurities such as B being doped in the gate electrode of a p-channel transistor and n-type impurities such as P and As being doped in the gate electrode of an n-channel transistor, are now being used to realize high performance of CYMOS transistors.
In order to form a low resistance contact to a small area of a semiconductor surface, silicide (salicide) techniques are used to form in a self-alignment manner a silicide (salicide) layer on the surface of a source/drain region (in some cases, also on a gate electrode). Incorporation of silicide techniques limits the conditions of succeeding thermal processes. This limitation can be eliminated also by forming an interlayer insulating film by PECVD or single wafer processing type thermal CVD.
Formation of an interlayer insulating film by a low temperature process poses a problem of diffusion of moisture from the interlayer insulating film into a MOS transistor structure. An etch stopper (self-align contact (SAC)) is desired when a contact hole is etched through an interlayer insulating film to a source/drain region which uses silicide. To this end, technologies of forming a lamination structure of a thin nitride film and an oxide film formed on the nitride film, as an interlayer insulating film, have been developed in which both the nitride and oxide films are formed by PECVD or single wafer processing type thermal CVD or a combination of these CVD processes. The nitride film provides a moisture impermeable function and an etch stopper function.
Formation of an interlayer insulating film by PECVD or batch thermal CVD is associated with new problems such as an instable threshold voltage of p-channel MOSFET and shortening of a lifetime of a p-channel MOSFET in terms of BT (bias temperature) stress and a lifetime of an n-channel MOSFET in terms of hot carriers. These problems become critical issues when high reliability semiconductor integrated circuit devices are to be manufactured.